1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and, more specifically, to an improved method and apparatus for chemical-mechanical polishing.
2. Description of Relevant Art
Integrated circuits manufactured today are made up of literally millions of active devices such as transistors and capacitors formed in a semiconductor substrate. Integrated circuits rely upon an elaborate system of metalization in order to connect the active devices into functional circuits. A typical multilevel interconnect 100 is shown in FIG. 1. Active devices such as MOS transistors 107 are formed in and on a silicon substrate or well 102. An interlayer dielectric (ILD) 104, such as SiO.sub.2, is formed over silicon substrate 102. ILD 104 is used to electrically isolate a first level of metalization which is typically aluminum from the active devices formed in substrate 102. Metalized contacts 106 electrically couple active devices formed in substrate 102 to the interconnections 108 of the first level of metalization. In a similar manner metal vias 112 electrically couple interconnections 114 of a second level of metalization to interconnections 108 of the first level of metalization. Contacts and vias 106 and 112 typically comprise a metal 116 such as tungsten (W) surrounded by a barrier metal 118 such as titanium-nitride (TiN). Additional ILD/contact and metalization layers can be stacked one upon the other to achieve the desired interconnection.
A considerable amount of effort in the manufacturing of modern complex, high density multilevel interconnections is devoted to the planarization of the individual layers of the interconnection structure. Nonplanar surfaces create poor optical resolution of subsequent photolithographic processing steps. Poor optical resolution prohibits the printing of high density lines. Another problem with nonplanar surface topography is the step coverage of subsequent metalization layers. If a step height is too large there is a serious danger that open circuits will be created. Planar interconnect surface layers are a must in the fabrication of modern high density multilevel integrated circuits.
To ensure planar topography, various planarization techniques have been developed. One approach, known as chemical-mechanical polishing, employs polishing to remove protruding steps formed along the upper surface of ILDs. Chemical-mechanical polishing is also used to "etch back" conformally deposited metal layers to form planar plugs or vias. In a typical chemical-mechanical polishing method, as shown in FIG. 2a, a silicon substrate or wafer 202 is placed face down on a rotating table 204 covered with a flat polishing pad 206 which has been coated with an active slurry 208. A carrier 200, which is typically made of thick nonflexible metal plate 214, is used to apply a downward force F.sub.1 from shaft 205 against the backside of substrate 202. A retaining ring 217 centers wafer 202 on carrier 200 and prevents it from slipping laterally. It is to be noted that retaining ring 217 is not in contact with polishing pad 206 during polishing. The backside of wafer 202 is typically pressed by a resilient carrier pad 212. The downward force F.sub.1 and the rotational movement of pad 206 together with the slurry facilitate the abrasive polishing and planar removal of the upper surface of the thin film. Carrier 200 is typically rotated by spinning shaft 205 to enhance polishing.
A problem associated with carrier 200 is the unequal polishing pressure distribution which can develop across the surface of wafer 202. Wafer 202 is pressed down by nonflexible metal plate 214 of carrier 200. Mechanics dictates that the integration of pressure of all of the areas of the front side of wafer 202 must equal the downward force applied to carrier 200. Therefore, in carrier 200, the pressure at any point on wafer 202 is controlled by the local compressive modulus (hardness) and local compression of polishing pad 206 and carrier pad 212. Any variation in the amount of compression of carrier pad 212 or polishing pad 206 results in local pressure variations. With carrier 200 any nonuniformities in wafer thickness and/or surface irregularities on wafer carrier 200 or polishing table 204 can create local pressure variations across the surface of wafer 202.
It is generally understood that the polish removal rate in chemical-mechanical polishing is directly proportional to the pressure (lbs/in.sup.2) applied between the wafer and the polishing pad in the direction perpendicular to the polishing motion. The greater the pressure, the greater the polish removal rate. Thus, nonuniform pressure distribution across the surface of wafer 202 creates a nonuniform polish rate across the surface of wafer 202. Nonuniform polishing can result in too much film being removed from some parts of wafer 202 and not enough film being removed from other parts. Nonuniform polishing can cause the formation of overly thin films and/or result in insufficient planarization, both of which degrade process yield and reliability. It is to be appreciated that chemical-mechanical polishing with a nonuniform polish rate is manufacturably unacceptable in the fabrication of today's high density, multi-level integrated circuits.
Another problem associated with present polishing techniques and wafer carrier 200 is the "edge rounding" effects which can result due to polishing pad bending. When wafer 202 is forcibly pressed against pad 206 during polishing, pad 206 compresses under wafer 202 and a bend 207 forms in pad 206 near the outer edge of wafer 202. The bend 207 causes a substantial increase in pressure along the very outer (approximately 0.1 inch) edge 216 of wafer 202. A high pressure area 216 is created where the bent pad touches wafer 202. Additionally, as a consequence of fundamental mechanical principles, a lower than normal polishing pressure area 218 is created directly inside high pressure area 216. Lower polishing pressure area 218 generally effects about the half inch diameter inside high pressure area 216 of wafer 202. A generally uniform polish pressure normally results over the remainder or center 220 of wafer 202. The polishing pressure discontinuity across the surface of wafer 202 due to pad bend 207 causes wafer 202 to have a relatively uniform thickness in the central region 220, surrounded by a substantially thicker region 218 which in turn is surrounded by a very thin outside edge 216. Essentially a thick ring is formed around the outside radius of wafer 202 when carrier 200 is used. FIG. 2b illustrates the polishing pressure distribution across the surface of wafer 202 when wafer carrier 200 is used.
Still yet another problem associated with wafer carrier 200 is that polish uniformity can be effected by "pad wear". As polishing pad 206 is used to polish a number of wafers, the initial flat surface becomes concave due to wear by the wafer's surface. A concave pad surface creates a nonuniform pressure distribution across the wafer diameter. A low pressure area is created at the center of the wafer where wear is greatest and a high pressure area is created on the outside area of the wafer where pad wear is the least. The effect is that the polishing removal rate decreases from the outside edge of the wafer to the center of the wafer. Shaped carriers have been proposed to counteract the concavity of the polishing pad. The manufacturing of shaped carriers, however, requires substantial skill as well as the ability to determine exactly what shape will create the most uniform wafers. Additionally, since pad surface topography changes over time, so must the shape of the carrier in order to provide a uniform polishing. As is expected, use of a shaped carrier is manufacturably inadequate to remedy the problems associated with pad wear.
Thus, what is needed is a novel method and apparatus for chemical-mechanical polishing a thin film formed on a semiconductor substrate where a uniform polish pressure is provided across the surface of the wafer regardless of polishing pad or table irregularities.